module led_flow(
    input   wire        sys_clk        ,
    input   wire        sys_rst_n      ,

    output  reg  [3: 0] led_out
);
parameter LED_NUM = 28'd50_000_000;
reg [27: 0] led_cnt;//计数寄存器
//设计计数器
always @(posedge sys_clk or negedge sys_rst_n) begin
    if(!sys_rst_n)begin
        led_cnt <= 28'd0;//计数器初始化为0
    end 
    else if(led_cnt == LED_NUM - 1)begin
        led_cnt <= 28'd0;
    end
    else begin
        led_cnt <= led_cnt + 28'd1;
    end
end
//设计LED灯
always @(posedge sys_clk or negedge sys_rst_n) begin
    if(!sys_rst_n)begin
        led_out <= 4'b0001;
    end 
    else if(led_cnt == LED_NUM - 1)begin
        led_out <= {led_out[2: 0], led_out[3]};
    end
    else begin
        led_out <= led_out;
    end
end
endmodule